Mentor Graphics Vista ESL Platform Takes Center Stage in Mentor's ESL
Strategy with Expanded Functionality
WILSONVILLE, Ore., Sept. 7, 2011 - Mentor Graphics Corporation
today announced it has expanded the VistaT ESL Platform to address the needs
for Virtual Prototyping for early software development. In addition, the
Vista ESL platform's integration with Catapult C, sharing common TLM
modeling style for Virtual prototyping and HLS-based hardware
implementation, has been strengthened with the MentorR partnership with
Calypto. The Vista ESL platform is the center point of the Mentor
comprehensive ESL strategy, a strategy that has extended the boundaries of
ESL technologies by addressing a broad range of electronic system design,
virtual prototyping, hardware realization, software realization, and
TLM-to-RTL verification and model reuse challenges.
Virtual Prototyping for Early Software Development
The Vista ESL platform provides the capability to create a Virtual Prototype
derived from the Virtual TLM Platform that retains its key hardware
attributes. The Vista Virtual Prototype can be used for firmware testing,
operating system integration and hardware-dependent application development.
Its TLM/ISS models are software binary compatible. Its scalable level of
abstraction allows very fast simulation speed for software validation, and
allows switching to more accurate Approximately Timed (AT) simulation during
run time for software performance and power optimization of the system.
Strengthened Partnership with Calypto
The move to higher levels of abstraction based on C and SystemC offers the
promise of better quality of results in a shorter amount of time. For
hardware implementation, the Vista ESL platform's tight integration with the
Calypto Catapult C high-level synthesis tool results in a complete TLM
2.0-based hardware implementation solution. This allows users to share a
single and consistent TLM modeling style. The Calypto TLM synthesis flow
supports converting abstract TLM models to pin-accurate, protocol-specific,
SystemC models, and from there, to synthesized to RTL code. Conversely, the
synthesized TLMs can be used in the Vista Virtual Platform for architectural
optimization of performance and power, and in the Vista Virtual Prototypes
for early software development.
"Mentor has a long track record of leading the quickly growing ESL market,
and we plan to continue on this path far into the future," said Walden C.
Rhines, chairman and CEO of Mentor Graphics. "Expanding the Vista Virtual
Prototyping capability for early software development-combined with
integration between Vista Virtual Prototyping and Sourcery CodeBench
embedded software development tools- is only one of the target areas for
growth. The newly announced acquisition of Catapult C by Calypto leverages
tool integrations that have existed for years, and further extends the
Mentor ESL offering into the Calypto ESL hardware realization flow."
About the Vista ESL Platform
- For architectural optimization, the Vista ESL platform delivers an
advanced electronic systems design and analysis environment for designing at
a level of abstraction above RTL. It allows creating scalable transaction
level models (TLMs), assembling them into a Virtual Platform, integrating
them with software, and simulating, analyzing and optimizing both hardware
and software for meeting performance and power design goals.
- The integration of Vista Virtual Prototyping with the Mentor Embedded
SourceryTM CodeBench unified embedded software development tools gives SoC
and system software developers the flexibility to debug, analyze and
optimize their systems software at early stages of the development process,
even before RTL implementation.
- For hardware implementation, the Vista ESL platform's tight integration
with the Calypto Catapult C tool results in a complete TLM 2.0-based
ESL-to-RTL implementation solution allowing users to share a single and
consistent TLM modeling style.
- For SoC and sub-system hardware/software verification, the Vista ESL
platform supports simulation, validation and debugging of hardware and
software errors. Its integration with Sourcery CodeBench to debug the
embedded OS booting firmware provides for early validation of the
application software on the Vista Virtual Prototype. The QuestaR Platform
and the Universal Verification Methodology (UVM) supports Vista TLM model
and Virtual Platform reuse, test plan tracking and accelerated coverage
closure. Furthermore, the Vista ESL platform can be combined with the
VeloceR hardware emulator to provide a hybrid virtual prototype with
accelerated RTL that is tested by the software running on the Vista ISS
models and is validated, debugged and analyzed using Sourcery CodeBench.