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Product News

Cadence Announces Advanced Silicon, Package, Board Co-Design Capabilities.

SAN JOSE, Calif., 25 Apr 2011 -- Cadence Design Systems, Inc. today introduced the latest version of its Allegro PCB and IC packaging technology, delivering new capabilities that provide a significant increase in both productivity and predictability across silicon, SoC and system development. New technologies include advanced miniaturization capabilities, uniquely integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design features, and flexible team-design enablement to address global designer productivity. The company also announced that the Allegro 16.5 technology will be available through product configuration that enables users to access advanced features on-demand for specific design tasks, thus optimizing total cost-of-ownership.

“Coming on the first anniversary of the announcement of the EDA360 vision, our Allegro 16.5 release strengthens the connection between Silicon, SoC and System Realization—the three key tenets of EDA360,” said John Bruggeman, senior vice president and CMO of Cadence. “We have leveraged our leadership in PCB and IC package design to drive a true end-to-end flow across all product creation disciplines, which speeds time to market while improving productivity and profitability for our customers.”

The new Allegro 16.5 features and capabilities are aimed at easing the path to co-design and analysis between engineers involved in Silicon, SoC, and System Realization, and enabling more predictable and efficient design flows that deliver higher-quality end products.

Allegro Offers a Constraint-driven Approach for System Realization
Assisting system developers, the Allegro 16.5 release provides many capabilities that enable a more productive, predictable path and closure to product creation. New in this version of Allegro is a constraint-driven flow for embedded components that employs advanced miniaturization techniques used in state-of-the-art products--such as smart phones, tablet PCs and avionics--to reach new levels of functional density. Traditionally, manual layout is used to place and route embedded components, but this is an error-prone process with multiple iterations and no design rule checking. The Allegro technology enables a simpler way to place and route these components with its constraint-driven approach. The new Allegro Power Delivery Network Analysis is seamlessly integrated with Allegro PCB Editor for comprehensive power trade-offs of fully routed PCBs.

Increasing use of standards-based interfaces such as DDR4 and PCI Express 3.0 is making timing closure on PCBs extremely challenging. The new PCB Interconnect Design Planning option uses a Cadence-patented hierarchical abstraction, coupled with semi-automatic approaches, that leverages feedback from the route engine to accelerate the path to timing closure.

The new concurrent team design authoring capability of Allegro also shortens the time it takes to create design intent by leveraging the power and skill of a distributed engineering team.

New DDR3 PCB Design Kit Advances SoC Realization
Selecting and integrating SoC IP that works with package and board implementations has always been a major challenge. Starting with Allegro 16.5, Cadence will extend SoC Realization by providing package-board-aware SoC IP. With this release, a package-board-aware DDR3 SoC IP methodology kit will be available to provide a compliant and fast implementation path from silicon IP to package and board. Similar support for other protocols, such as the recently announced DDR4 memory standard, will come in the future, according to Cadence.



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