Oasys Design Systems Enhances Chip Synthesis with Power Capabilities
New Power Synthesis Feature Re-Synthesizes from RTL
with Power Constraints, Supports CPF, UPF Support to Come
SANTA CLARA, CALIF. –– February 24, 2011
— Oasys Design Systems today unveiled the latest version
of its revolutionary Chip Synthesis platform with enhanced
capabilities that include chip-level power analysis and the
ability to re-synthesize a design from the register transfer
level (RTL) with new power constraints.
“Power is now the toughest design constraint,”
asserts Paul van Besouw, Oasys’ president and chief
executive officer (CEO). “Traditional synthesis tools
can’t handle power in ways that are effective for project
teams because power is a chip-level problem not a block-level
RealTime Designer allows power to be managed at the chip level
and gives project teams a way to re-synthesize an existing
RTL design to take into account a new power architecture.
It can read input files from the Common Power Format (CPF)
from Si2, the way low-power policies are described, and will
soon support IEEE Standard 1801-2009, based on Accellera’s
Unified Power Format (UPF). It also supports multiple voltage
threshold optimization and clock gating.
“CPF has enjoyed widespread industry adoption, with
strong support from industry leaders and emerging companies
such as Oasys Design Systems,” says Steve Schulz, president
and CEO of Si2. “I am confident their investment in
CPF will continue to reap increasing dividends as the Low-Power
Coalition advances CPF, for example the numerous powerful
capabilities just released in CPF 2.0.”
The tool offers a way for designers to experiment with voltage
levels and power tradeoffs at the architectural level for
maximum impact, while taking all power measurements from a
fully placed netlist. During synthesis, RealTime Designer
inserts all the appropriate level shifters, isolation cells
and retention registers, as specified in the power policy.
It is not necessary to have a complete CPF or UPF file before
using RealTime Designer. Instead, the power policy can be
explored for various scenarios and RealTime Designer can be
used interactively to consider alternative power policies
without needing them to be fully specified in an external
file. When this “what-if” analysis is complete
and the final policy has been selected, RealTime Designer
will write out the CPF or UPF file to be used by other tools,
such as analysis and verification, and traditional place and
Chip Synthesis is a fundamental shift in how synthesis is
applied to the design and implementation of integrated circuits
(ICs). Traditional synthesis, with its limited capacity, forces
power to be considered at the level of each individual block,
and some master plan to be created to allocate the power budget
among those blocks without really having any good information
Block level tools do a poor job of handling chip-level issues.
RealTime Designer is the first design tool for physical register
transfer level (RTL) synthesis of 100-million gate designs.
It features a unique RTL placement approach that eliminates
unending design closure iterations between synthesis and layout.
RealTime Designer follows a “Place First” methodology
that takes RTL, partitions it into blocks, places the RTL
in the context of a floorplan and implements each block all
the way to placement. Chip-level constraints are automatically
propagated across the blocks and the design is optimized for
the best possible quality of results. During the optimization
phase, RealTime Designer will repartition the design at the
RTL and re-implement it until chip-level constraints are met.
Availability and Pricing
The latest version RealTime Designer is shipping now and is
priced from $395,000 (U.S.) for a one-year, time-based license.